Altera Corporation (NASDAQ: ALTR) today announced fourth quarter sales of $479.9 million, down 4 percent from the third quarter of 2014 and up 6 percent from the fourth quarter of 2013. Fourth quarter net income was $111.1 million, $0.36 per diluted share, compared with net income of $118.0 million, $0.38 per diluted share, in the third quarter of 2014 and $98.9 million, $0.31 per diluted share, in the fourth quarter of 2013.
Cash flow from operating activities in 2014 was $666.2 million. Altera repurchased approximately 4.3 million shares during the quarter at a cost of approximately $151.5 million.
Altera’s board of directors has declared a quarterly cash dividend of $0.18 per share, to be paid on March 2, 2015 to stockholders of record on February 10, 2015.
“We grew 12 percent in 2014, outpacing the semiconductor industry,” said John Daane, president, chief executive officer, and chairman of the board. “Our Arria 10 FPGAs, the first of our Generation 10 products, are proving to be competitively quite strong with good design-win momentum and record opportunities to pursue. We are entering the advanced stages of design for our high-end Stratix 10 FPGA, the industry’s only 14 nanometer FinFET-based FPGA, with planned introduction later this year.”
Several recent accomplishments mark the company’s continuing progress:
- Audi has selected Altera’s SoC field-programmable gate arrays (FPGAs) for use in Audi’s advanced driver assistance system (ADAS) targeted for mass production. Audi, a self-driving car technology leader, chose Altera’s Cyclone® V SoC FPGAs for their ability to increase system performance and enable the differentiated features Audi requires for piloted driving and parking that are not available with application specific standard product solutions. Altera’s Cyclone V SoC FPGAs combine programmable logic with dual-core ARM® Cortex™-A9 processors that allow ADAS platform designers to customize the hardware and software running in their products. This combination provides powerful building blocks to accelerate algorithms commonly used in ADAS designs. Audi’s zFAS control unit is the industry’s first fully centralized ADAS module that processes all self-driving functions in a single unit, unlike other architectures which have multiple modules distributed throughout the vehicle.
- Altera and IBM have unveiled the industry’s first FPGA-based acceleration platform that coherently connects an FPGA to a POWER8 CPU leveraging IBM’s Coherent Accelerator Processor Interface (CAPI). The reconfigurable hardware accelerator significantly improves system performance, efficiency and flexibility in high-performance computing (HPC) and data center applications. FPGA-accelerated POWER8 systems are optimized to enable compute- and processing-intensive tasks required in next-generation HPC and data center applications, including data compression, encryption, image processing and search. Using CAPI to coherently attach FPGA accelerators to the fabric of a POWER8 processor and main system memory make the FPGA appear as simply another core on the POWER8 processor. This results in shortened development time by greatly reducing lines of software code and reduced processor cycles versus conventional IO attached accelerators.
- Electronics Weekly magazine selected the Altera Software Development Kit (SDK) for OpenCL as its design tool of the year at the annual Elektra European Electronics Industry Awards ceremony in London. The Elektra Awards are presented to companies whose products demonstrate advanced technical capabilities and usefulness as determined by a panel of independent industry experts and representatives from Electronics Weekly. These accolades represent the latest in a series of awards and recognitions the Altera SDK for OpenCL has received since its release in 2012. The Altera SDK for OpenCL allows programmers to rapidly develop algorithms with the OpenCL language and harness the performance and power efficiencies of FPGAs. Today, Altera offers the industry’s only OpenCL-conformant solution that allows software programmers to easily implement OpenCL applications on FPGA accelerators.