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Due to the growth of the semiconductor business, the wider adoption of Cu pillar solutions and the introduction of flip chip technology for LED and CMOS image sensors (CIS) applications, the flip chip market is expanding. However, market research firm Yole Développement (Yole) expects flip chip capacity will max out by 2017, requiring new investment in the technology by 2018.
“Flip chip assembly technology provides various benefits such as high I/O counts, fine pitch interconnection, and superior electrical and thermal performance,” explains Thibault Buisson, technology and market analyst, advanced packaging at Yole. “This drives its application across specific segments.”
The maximum growth in flip-chip bumping capacity will come from Cu pillars, driven by the finer pitches, higher I/O counts, lithography nodes below 28nm, emergence of 2.5D/3D packaging, increased current density and thermal dissipation needs. In the meantime lead-free solder bumping is expected to grow at just 2 percent CAGR as outsourced semiconductor assembly and test (OSATs) companies and foundries convert their existing solder bumping lines to Cu pillar lines. With the scaling of the flip chip pitch, OSATs are presently pushing the envelope of C2 mass reflow bonding with capillary underfill to pitches as low as 50µm by formulating engineered materials and improving assembly processes. However, if the pitch reaches or falls below 40µm thermo compression bonding (TCB) will be the key option because of its high placement accuracy.
TCB will be adopted first in high volume manufacturing by IDMs like Intel, who can bear the high cost of ownership, followed by memory suppliers for their next generation memories based on through-silicon via technology.
“Intel has recently qualified ASM’s high throughput TCB bonder for assembly of 14nm chips for their CPUs in applications such as data centers, servers, and high-end computing,” said Santosh Kumar, senior technology and market analyst, advanced packaging at Yole. “At Yole, we estimate flip chip bonders’ total market value will reach $435 million in 2020, with a CAGR of 7 percent,” he added. “Flip chip bonders and underfill materials will become key in coming years.”
Since Cu pillar processing can be performed by standard foundries and IDMs, the supply chain may see some slight modification, reports Yole in “Flip Chip: Technologies & Market Trends.” Yole’s analysts expect higher investment in Cu pillar 12” line wafer bumping lines from wafer foundries such as TSMC and SMIC. This change will affect domestic OSAT wafer bumping revenue since foundries will gain market share.
OSATs will maintain their strong position in wafer bumping and assembly thanks to of their huge experience and low cost solutions, Yole believes. Their business model enables them to better control the supply chain, as they provide for the complete set of flip-chip services: package design and qualification, wafer bumping, substrate in-sourcing, assembly and final test.
However, big IDM companies such as Intel and Samsung maintain their dominance in terms of wafer bumping capacity. “At Yole, we expect that even in 2020 Intel will remain the highest-capacity player in Cu pillar wafer bumping,” said Buisson.
Foundries and OSATs are also establishing joint ventures for wafer bumping to provide turnkey solutions to customers from chip fabrication to assembly at competitive cost. Chinese players are significantly increasing their presence in wafer bumping and flip chip assembly by mergers and acquisitions: JCET acquired STATS ChipPAC and FCI was acquired by Tianshui Huatian Technology Company, Yole reports.
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