The proliferation of tighter microvia densities and signal integrity requirements in printed boards within the electronics industry has revealed reliability concerns with microvia structures in high performance products. A number of IPC OEM member companies have approached IPC with examples of microvia failures in high-profile hardware that were not observed until after bare printed board fabrication, inspection and acceptance, including:
- Post Reflow In-Circuit Test
- During “Box Level” Assembly Environmental Stress Screening (ESS)
- In Service (End Customer Fielded Product)
Many of these failures occurred within products that had already passed traditional production lot acceptance testing in accordance with existing IPC-6010, Printed Board Qualification and Performance Specifications. IPC has been provided with data showing that traditional inspection techniques utilizing thermally stressed microsections and light microscopes alone is no longer an effective quality assurance tool for detecting microvia-to-target plating failures.
Related to this, in 2018, IPC released IPC-WP-023, an IPC Technology Solutions White Paper on Performance-Based Printed Board OEM Acceptance titled “Via Chain Continuity Reflow Test: The Hidden Reliability Threat – Weak Microvia Interface.” The white paper asserts stacked microvia reliability problems linked to a weak interface between microvia target pads and electrolytic copper fill and provides data in support of the observations reported by numerous IPC OEM member companies.
As a result of IPC-WP-023, the IPC V-TSL-MVIA Weak Interface Microvia Failures Technology Solutions Subcommittee was formed in late 2018 to begin investigating the potential causes of these failures and to provide industry resources on the topic. This group provided its first update to industry during an open forum held during IPC APEX EXPO 2019 and will continue to provide updates as it progresses.
In response to this, IPC is issuing the following warning statement, which will also be included in the forthcoming IPC-6012E, Qualification and Performance Specification for Rigid Printed Boards:
“There have been many examples of post fabrication microvia failures over the last several years. Typically, these failures occur during reflow, however they are often undetectable (latent) at room temperature. The further along the assembly process that the failures manifest themselves the more expensive they become. If they remain undetected until after the product is placed into service, they become a much greater cost risk, and more importantly, may pose a safety risk.”
Looking forward, IPC is working on the concept of moving away from traditional microsection evaluations and focusing on performance-based acceptance testing, a recommendation made several years ago by the IPC D-33a Rigid Printed Board Performance Task Group responsible for the IPC-6012 specification. In conjunction with this task group and the IPC 1-10c Test Coupon and Artwork and Generation Task Group and D-32 Thermal Stress Test Methodology Subcommittee, IPC continues to work on revisions to its existing test methods for thermal stress (IPC-TM-650, Method 2.6.27) and thermal shock (IPC-TM-650, Method 22.214.171.124). These methodologies make use of performance-based acceptance test coupons utilizing electrical resistance measurements, such as the IPC-2221B Appendix “D” coupon, which when designed properly in accordance with the IPC-2221B Gerber Coupon Generator tool, have allowed manufacturers to detect latent microvia failures and shelter themselves from possible defect escapes.
For more information on this issue, contact John Perry, director, printed board standards & technology, at JohnPerry@ipc.org.