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The latest in a series of Pentagon semiconductor initiatives seeks to embed security features into chip designs that would allow silicon architects to probe economics-versus-security tradeoffs while baking in security throughout device lifecycles.
The chip design effort represents continuing U.S. efforts to secure its electronics supply chain as semiconductors emerge as a choke point in what is shaping up as a technological Cold War with China.
Source: DARPA
DARPA announced two teams this week to ramp up its year-old Automatic Implementation of Secure Silicon (AISS) program led by Synopsys and Northrop Grumman. Both teams will develop Arm-based architectures that incorporate a “security engine” used to defend against attacks and reverse-engineering of chips. An upgradeable platform would provide the infrastructure that military planners say is needed to manage hardened chips throughout their lifecycles.
Launched in April 2019, AISS is designed to balance security and economic considerations in securing the IC design process and chip supply chains.
Besides Arm, the Synopsys team includes aerospace giant Boeing, the University of Florida’s Institute for Cybersecurity, Texas A&M University, University of California at San Diego, and U.K.-based embedded analytics vendor UltraSoC.
Northrop Grumman heads a team that includes IBM, University of Arkansas and University of Florida.
The two-tiered effort includes competing “security engine” approaches that address key chip vulnerabilities such as side channel attacks, hardware Trojans, reverse engineering and supply chain exploits. Side channel attacks include tracking device power consumption as a means of stealing an encryption key.
The project also has implications in anti-counterfeiting efforts, which have largely focused on the traceability of chips to their factories.
In a later phase, the Synopsys team will seek to leverage EDA tools to integrate its security engine into SoC platforms. The approach would combine “security-aware” EDA tools developed under the DARPA program using commercial IP from Arm, Synopsys and UltraSoC.
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