Top 9 Chip Design Challenges

As we evaluate the system-on-a-chip (SoC) design landscape, the industry continues to search for solutions to a long list of design challenges and issues. They include the following. Rising cost: SoC silicon and software design costs are rising at each new process node, with increasing emphasis now being placed on the software side of the…

EDA World Embracing IP Subsystems

After attending the 48th Design Automation Conference in San Diego last week, it was clear to me that the discussion around the trend towards IP Subsystems is real and has substance behind it. In fact, several IP and EDA vendors were discussing this idea, including Sonics, Synopsys, Cadence, Atrenta, ChipStart, and eSilicon, to name a…